1. Field of the Invention
The present invention relates to a delay device, a semiconductor testing device, a semiconductor device, and an oscilloscope and in particular to a delay device, a semiconductor testing device, a semiconductor device, and an oscilloscope provided with an addition circuit that applies a predetermined voltage to a delay element.
2. Description of the Related Art
FIG. 1 shows the delay device D 12 as a related art. The delay device D12 includes a plurality of delay elements DL in series with each other. The incoming transmission signal is delayed by each delay element DL producing a delay time of Td.
FIG. 2 shows the current that flows in the delay device D12. Once a unit pulse is fed to the delay device D12 as shown in FIG. 2(A), the current applied to the delay element DL changes to flow in a burst as shown in FIG. 2(B). The period of time during which the current flows is equivalent to the delay time Td. When successive pulses are fed to the delay device D12 as shown in FIG. 2(C), whilst the initial current generated by the first pulse flows, another current generated by the following pulse also flows, as shown in FIG. 2(D). When the current of two or more delay elements DL simultaneously changes in this way, the sum of the current flowing in the delay device D12 changes as shown in FIG. 2(E). Since the change in the current alters the power supply voltage Vdd and Vss of the delay device D12, the accuracy of the delay time Td of the delay device D12 is decreased.
FIG. 3 shows another delay device D12 as a related art. The delay device D12 includes a plurality of selectors SEL in series with each other, and a plurality of delay elements DL each of which delay the incoming transmission signal and feed it to a following selector SEL. The delay element DL has one or more inverters in series with each other. The selector SEL selectively outputs the signal that passes through the delay element DL as well as the signal that does not pass through. The timing of the electric power consumed in the delay device D12 differs depending upon the selection by the selector SEL. For example, if all the selectors SEL select the outputs of the delay elements DL, the transmission signal advances slowly; accordingly, when the selector SEL closest to the output terminal consumes the electric power, the selector SEL closest to the input terminal also consumes the electric power. That is, the electric power is consumed at two or more selectors SEL. The end result is a reduction in accuracy of delay time because the power supply voltage of the delay device D12 differs when the electric power is consumed at two or more selectors SEL compared to when consumed at only one selector SEL.
FIG. 4 shows a circuit electrically equivalent to the delay element DL of FIG. 3. A wiring capacitance CL arises in the signal line LIN that connects the drive circuit DR and the receipt circuit RC while an input capacitance CG arises at the input terminal of the receipt circuit RC. The input capacitance CG is proportional to the number of receipt circuits RC to be connected, while the wiring capacitance CL is proportional to the length of the signal line LIN. If the input capacitance CG and the wiring capacitance CL are increased, permitting the delay device D12 to pass the signal requires a larger current. The increase in the current enlarges the change in the current as shown in FIG. 2(E), thus decreasing the accuracy of the delay time Td.
If the power supply voltage sharply changes due to the operation of the drive circuit DR, an electromagnetic wave noise is radiated. If the change in the power supply current and power supply voltage increases because the signal line LIN is long, the electromagnetic wave noise radiated from the delay device D10 increases also. The electromagnetic wave noise radiated from the electronic instrument must be below a given level, so it is therefore necessary to prevent the electromagnetic wave noise from arising in the electronic instrument provided with the delay device D10.